The present invention relates to an X shaped ROM semiconductor memory device hereinafter referred to as an X-ROM memory device, and may be applied particularly to an improved X-ROM to improve the density of integration when fabricating a mask ROM and an erasable and programmable ROM.
Conventionally, an X-ROM contact region can hold a plurality of cells arranged in the shape of an X, with their center on a contact region.
Accordingly, X-ROM semiconductor memory devices are widely used to increase the density of integration.
FIG. 1 shows a structure of a standard mask ROM to store information permanently by using a mask in accordance with the prior art.
As shown in FIG. 1, a ROM comprises a plurality of cell transistors, each having a storage capacity of 1 bit, a word line connected to the cell transistors, a GND (ground) line connected to each of the cell transistors, and a plurality of bit lines and contact regions for connecting to each of the cell transistors.
Herein, FETs (Field-Effect Transistors) are utilized as the cell transistors.
The density of integration of said mask ROMs is not optional, since a contact region is required to be respectively formed for each cell transistor as illustrated in FIG. 1.
FIG. 2 is a layout diagram of an X-ROM that improves the density of integration. In it, the word lines 1 are successively arranged horizontally at regular intervals in the vertical direction and cell transistors Q (herein FETs are utilized as cell transistors) are successively connected to each word line 1 at regular intervals in the horizontal direction. The changeable, or switchable ground line 3 and the bit line 2 are successively arranged in turn perpendicularly crossing each word line 1. Contact regions 4 are formed between word lines to hold four transistors in common concurrently.
In FIG. 2, the hatched regions are used to denote an active semiconductor region formed in accordance with standard practice.
FIG. 3 is a partial circuit of the portion of an X-ROM corresponding to a representative one word line as illustrated in FIG. 2. In FIG. 3, the cell transistors Q are successively arranged in turn through the contact region 4. Each cell transistor is successively connected to: (i) a word line 1 at regular intervals, (ii) a changeable GND line 3, and (iii) a the bit line 2.
Each sense amplifying cell transistor Qc is connected to the corresponding bit line 2. The driving cell transistors Qa are respectively connected to the corresponding odd changeable GND lines 3 and the driving cell transistors Qb are connected to the even changeable GND lines 3.
Accordingly, the required lines among the changeable GND lines 3 are grounded by the control signals S1 and S2 applied to gates of the driving cell transistors Qa and Qb. Other lines are floating or precharged with the predetermined voltage from a separate circuit which is not shown.
Herein, control signals S3 through S5 are applied to the gates of the sense amplifying cell transistors Qc to output only the output signals of those cell transistors Qc corresponding to the designated address.
As aforesaid, the GND lines of such an X-ROM in the prior art are referred to as changeable or switchable GND lines, since only the required GND lines are selected by control signals S1 and S2 to be grounded.
Furthermore, as shown in FIG. 2, because one contact region 4 is commonly in use for the four cell transistors formed around it in the shape of an X, the density of integration of the prior art X-ROM is higher than that of a conventional H-ROM.
In FIG. 2 and FIG. 3, the word line 1 is made of polysilicon and the bit line 2 and the changeable GND line are made of metal.
The hatched region of FIG. 2 shows the active semiconductor region. Cell transistors formed in the active region, the word line 1, the bit line 2, and the changeable GND line 3 are connected to each other by the active region.
The operation of conventional X-ROMs having the aforesaid structure will be described in more detail.
First, if control signal S1 or S2 is applied to the gates of the driving cell transistors Qa or Qb, the odd or even changeable GND lines 3 are respectively selected. Then charges which are precharged between the cell transistor Q and the bit line 2 with the predetermined voltage from the separate circuit are discharged to the selected changeable GND line 3 through the corresponding cell transistor.
At this time, the voltage state is dropped in the bit line 2 and the voltage drop state is sensed in its low level state by the sense amplifying cell transistors which correspond to the selected changeable GND lines 3 connected to outputs of bit lines 2.
Conversely, when the ROM is programmed to prevent current flow through the cell transistors Q, no voltage drop is generated in the bit line 2 and the high level state is sensed by the sense amplifying cell transistors Qc.
The method used for programming said cell transistors Q consists of enhancing the threshold voltage by injecting the charge to the floating gate as in an erasable and programmable ROM using a floating gate. The partial circuit of the X-ROM as shown in FIG. 3 utilizes the method of removing the active region as the method for programming said cell transistors.
As above-mentioned, the structure of the prior art X-ROM as shown in FIG. 2 and FIG. 3 can improve the density of integration of the device as compared with a conventional H-ROM, since four transistors, each of which is connected to a word line 1, are formed to share one contact region.
But, because the same metal conductive material is used for both the bit line 2 and the changeable GND line 3 in the prior art X-ROM, they need to be formed at regular intervals. Accordingly, because of this inherent constraint there is a limit to reduction of the design dimensions, so that the highest-density of integration cannot be achieved.
Furthermore, because the selecting cell transistors are each connected to a corresponding changeable GND line, the most effective highest-density integration cannot be achieved.